Method for manufacturing embedded memory with different spacer widths
US6248623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.