Method of fabricating an ONO dielectric by nitridation for MNOS memory cells

US6248628A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Arvind Halliyal · Cupertino, US
• David K. Foote · San Jose, US
• Hideki Komori · Tokyo, JP
• Kenneth Wo-Wai Au · Fremont, US

Key dates

• Filing date: Oct 25, 1999
• Grant date: Jun 19, 2001
• Expiry date: Oct 25, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes providing a semiconductor substrate and thermally growing a first silicon oxide layer overlying the semiconductor substrate. A thermal anneal is performed after growing the first silicon oxide layer in an ambient atmosphere of at least one of nitric oxide, nitrous oxide and ammonia. In this regard, nitrogen is incorporated into the first silicon oxide layer which leads to a better performance and a higher quality of the ONO structure. A silicon nitride layer is formed to overlie the first silicon oxide layer; and a second layer of silicon oxide is formed to overlie the silicon nitride layer to complete the ONO structure.