Arvind Halliyal
82Patents
28h-index
67Co-inventors
91Inventor score
Filing activity: May 13, 1992 → Oct 26, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6674138B1 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices | Electricity | 256 | Expired |
| US6642573B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Emerging Cross-Sectional Technologies | 174 | Expired |
| US6586349B1 | Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices | Electricity | 164 | Expired |
| US6451641B1 | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material | Electricity | 110 | Expired |
| US6803272B1 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Electricity | 108 | Expired |
| US7115469B1 | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process | Electricity | 95 | Expired |
| US6740605B1 | Process for reducing hydrogen contamination in dielectric materials in memory devices | Electricity | 83 | Expired |
| US6750066B1 | Precision high-K intergate dielectric layer | Electricity | 83 | Expired |
| US6645882B1 | Preparation of composite high-K/standard-K dielectrics for semiconductor devices | Electricity | 82 | Expired |
| US6949433B1 | Method of formation of semiconductor resistant to hot carrier injection stress | Emerging Cross-Sectional Technologies | 81 | Expired |
| US6670241B1 | Semiconductor memory with deuterated materials | Electricity | 66 | Expired |
| US6642066B1 | Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer | Electricity | 64 | Expired |
| US6265268A | High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device | Electricity | 63 | Expired |
| US6406960B1 | Process for fabricating an ONO structure having a silicon-rich silicon nitride layer | Emerging Cross-Sectional Technologies | 60 | Expired |
| US6563183B1 | Gate array with multiple dielectric properties and method for forming same | Electricity | 57 | Expired |
| US7033957B1 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Emerging Cross-Sectional Technologies | 42 | Expired |
| US6958511B1 | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | Electricity | 42 | Expired |
| US6593748B1 | Process integration of electrical thickness measurement of gate oxide and tunnel oxides by corona discharge technique | Chemistry; Metallurgy | 40 | Expired |
| US6248628A | Method of fabricating an ONO dielectric by nitridation for MNOS memory cells | Electricity | 40 | Expired |
| US6617215B1 | Memory wordline hard mask | Electricity | 39 | Expired |
| US6752899B1 | Acoustic microbalance for in-situ deposition process monitoring and control | Chemistry; Metallurgy | 38 | Expired |
| US6319775A | Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device | Electricity | 37 | Expired |
| US6410388B1 | Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device | Electricity | 36 | Expired |
| US6653191B1 | Memory manufacturing process using bitline rapid thermal anneal | Electricity | 35 | Expired |
| US6949481B1 | Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device | Electricity | 33 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.