Process for fabricating a flash memory device
US6248629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
A method for manufacturing a non-volatile memory device, the device having a core memory cell region and a periphery region, comprising the steps of: forming memory cell gate structures in the core memory cell region; forming active regions adjacent to the gate structure through a blanket implant; forming an implant/etch mask; implanting an impurity into one of the active regions; etching an oxide layer in the implant region; and forming active devices in the periphery region. In a further aspect, the method comprises method of performing a self aligned source etch in forming a memory device, comprising: forming resist spacers adjacent to the channel regions of the memory device; and etching the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.