Low cost method of fabricating transient voltage suppressor semiconductor devices or the like

US6248651A · kind A · utility

Assignee

• General Semiconductor, Inc. · US

Inventors

• Jack Eng · Freeport, US
• Joseph Chan · San Francisco, US
• Gregory Zakaluk · Seaford, US
• John Amato · Tracy, US
• Dennis Garbis · Huntington Station, US

Key dates

• Filing date: Jun 24, 1998
• Grant date: Jun 19, 2001
• Expiry date: Jun 24, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/2252
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.