Switching circuit for transference of multiple negative voltages
US6249458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.