Method and structure for testing embedded memories
US6249889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for testing embedded memories in an integrated circuit chip having a microprocessor core therein. The method includes the steps of testing the microprocessor core by applying a test pattern and evaluating the resultant output of the microprocessor core, and confirming an integrity of the microprocessor core prior to testing the embedded memory, applying an object code of assembly language test program to the microprocessor core from a source external to the integrated circuit chip, generating a memory test pattern by the microprocessor core based on the object code of the assembly language test program, and applying the memory test pattern to the embedded memory and evaluating the resultant response of the memory by comparing the response with the expected data by the microprocessor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.