Method and structure for testing embedded cores based system-on-a-chip
US6249893A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Jun 19, 2001 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.