Method of fabricating a DRAM storage node on a semiconductor wafer
US6251725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Jun 26, 2001 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole. A second dry etching process is used to etch the second conductive layer using the photo resist layer as a mask so as to form the storage node. Finally, the photo resist layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.