Method to form, and structure of, a dual damascene interconnect device

US6252290A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Shyue Fong Quek · Petaling Jaya, MY
• Ting Cheong Ang · Shanghai, CN
• Lap Chan · San Francisco, US
• Sang Yee Loong · Singapore, SG

Key dates

• Filing date: Oct 25, 1999
• Grant date: Jun 26, 2001
• Expiry date: Oct 25, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2221/1026
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and pattern…