Polysilicon structure and process for improving CMOS device performance
US6255200A · kind A · utility
0Cited by
16References
9Claims
0Family size
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Key dates
| Filing date | May 17, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 17, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/122
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A process for depositing polycrystalline silicon, including exposing a semiconductor substrate on which the polycrystalline silicon is to be deposited to a silicon containing gas and a temperature of about 680.degree. C. to about 800.degree. C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.