Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
US6255214A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1999 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Feb 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process amorphizes the semiconductor material in the gate and source/drain junctions prior to the deposition of the metal during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, non-dopant material, such as silicon or germanium, is implanted into the semiconductor material in an unmasked implantation procedure. This highly controllable implanting creates amorphous silicon regions with a substantially smooth interface with the crystalline silicon. When the silicide regions are formed during subsequent annealing steps, the silicide forms in a manner that follows the amorphous regions so that the silicide/silicon interface is also substantially smooth and junction leakage induced by silicidation is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.