DRAM cell configuration and method for its production

US6255684A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Roesner · Austin, US
• Lothar Risch · Neubiberg, DE
• Franz Hofmann · Munich, DE

Key dates

• Filing date: May 4, 1998
• Grant date: Jul 3, 2001
• Expiry date: May 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/395

Abstract

A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F.sup.2. F is a minimum structure size which can be produced by using the respective technology.