Patent · US Expired

Integrated memory having memory cells disposed at crossover points of word lines and bit lines

US6256219A · kind A · utility

0Cited by

5References

2Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Schrogmeier · Hersbruck, DE
Stefan Dietrich · Potsdam, DE
Sabine Schoniger · Hersbruck, DE
Christian Weis · Scheidegg, DE

Key dates

Filing date	Jun 7, 2000
Grant date	Jul 3, 2001
Priority date	—
Expiry date	Jun 7, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/1006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has first control lines, which run in the direction of bit lines, and a second control line, which runs in the direction of word lines. First control inputs of in each case at least two switching elements that are connected to different sense amplifiers are connected to the same first control line. The second control inputs of the switching elements are connected to the second control line. The invention makes it possible to reduce the number of first control lines running in the direction of the bit lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.