Low skew differential receiver with disable feature
US6256234A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | May 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock receiver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.