Apparatus for testing memories with redundant storage elements
US6256757A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Jul 3, 2001 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a host computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also counts of the number of memory cells of each row and column that are defective. After the test the counts are supplied to the host computer. When the host computer is unable to determine how to allocate the spare rows and columns from the counts alone, it requests the tester to process the data in the ECM to determine and supply the host computer with addresses of the defective memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.