Selective salicide process by reformation of silicon nitride sidewall spacers

US6258648A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventor

• Yong Meng Lee · Singapore, SG

Key dates

• Filing date: Feb 8, 1999
• Grant date: Jul 10, 2001
• Expiry date: Feb 8, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0227

Abstract

A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which exhibit low sheet rho lines and contacts, while blocking salicide formation on the sensitive memory FET's which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures exhibit low leakage and lack leakage problems caused by bridging, silicide ribbons or stringers.