Formation of electrical interconnect lines by selective metal etch
US6258709A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2000 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for the formation of electrical interconnect lines by a selective metal etch to form electrical interconnections between different layers in a semiconductor device is provided. The process eliminates the need to form vias between conductive layers in the structure by etching through an oxide layer. The resulting structure provides superior electrical contacts between electrically conductive features on different layers of a semiconductor device. Additionally, the process produces self-aligned vias, thereby eliminating misalignment problems and the need to pattern surrounds onto the M1 layer in a semiconductor stack or any other lower level metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.