Terrence B. McDaniel
31Patents
6h-index
36Co-inventors
69Inventor score
Filing activity: Aug 3, 1999 → Sep 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6350679B1 | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry | Electricity | 203 | Expired |
| US7517754B2 | Methods of forming semiconductor constructions | Electricity | 33 | Active |
| US7341909B2 | Methods of forming semiconductor constructions | Electricity | 25 | Expired |
| US7491641B2 | Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line | Electricity | 19 | Active |
| US6258709A | Formation of electrical interconnect lines by selective metal etch | Electricity | 14 | Expired |
| US7445996B2 | Low resistance peripheral contacts while maintaining DRAM array integrity | Electricity | 9 | Expired |
| US11393908B1 | Methods of forming a microelectronic device, and related microelectronic devices, memory devices, and electronic systems | Electricity | 5 | Active |
| US6844255B2 | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry | Electricity | 5 | Expired |
| US8580666B2 | Methods of forming conductive contacts | Electricity | 4 | Active |
| US7119024B2 | Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device | Electricity | 4 | Expired |
| US7902057B2 | Methods of fabricating dual fin structures | Electricity | 4 | Active |
| US7364966B2 | Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same | Electricity | 3 | Active |
| US7118966B2 | Methods of forming conductive lines | Electricity | 2 | Expired |
| US7605033B2 | Low resistance peripheral local interconnect contacts with selective wet strip of titanium | Electricity | 2 | Expired |
| US11488981B2 | Array of vertical transistors and method used in forming an array of vertical transistors | Electricity | 2 | Active |
| US7501672B2 | Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device | Electricity | 2 | Active |
| US7935997B2 | Low resistance peripheral contacts while maintaining DRAM array integrity | Electricity | 1 | Active |
| US11282548B1 | Integrated assemblies and methods forming integrated assemblies | Electricity | 1 | Active |
| US8026542B2 | Low resistance peripheral local interconnect contacts with selective wet strip of titanium | Electricity | 1 | Active |
| US11309315B2 | Digit line formation for horizontally oriented access devices | Electricity | 1 | Active |
| US7800137B2 | Semiconductor constructions | Electricity | 0 | Active |
| US8772163B2 | Semiconductor processing method and semiconductor structure | Electricity | 0 | Active |
| US7329618B2 | Ion implanting methods | Electricity | 0 | Expired |
| US12336288B2 | Array of vertical transistors and method used in forming an array of vertical transistors | Electricity | 0 | Active |
| US12069848B2 | Sense line and cell contact for semiconductor devices | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.