Apparatus and method of encapsulated copper (Cu) Interconnect formation
US6259160A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Apr 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the formation of a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed over a substantially completed semiconductor device on which a first sidewall metallic barrier, consisting of metallic material, such as tantalum (Ta), tantalum nitride (TaN) and tungsten nitride WN, is formed to line the wall structure of a via. The metallic liner encapsulates a first, substantially thin (.ltoreq.0.25 .mu.m) copper interconnect structure. A second selectively formed thicker (>>0.25 .mu.m) copper interconnect trench structure is formed overlying and integral with the first copper interconnect structure. A second metallic barrier, consisting of CoWP (cobalt-tungsten-phosphide) is deposited over the second selectively formed copper interconnect structure and is formed integral with the first sidewall metallic barrier. The fully encapsulated copper interconnect structure can be further processed to spin coat a second low dielectric constant material layer …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.