Integrated memory having sense amplifiers disposed on opposite sides of a cell array
US6259641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.