Thomas Rohr
29Patents
7h-index
19Co-inventors
58Inventor score
Filing activity: Nov 15, 1999 → Sep 29, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6468896B2 | Method of fabricating semiconductor components | Emerging Cross-Sectional Technologies | 21 | Expired |
| US7233515B2 | Integrated memory arrangement based on resistive memory cells and production method | Electricity | 15 | Expired |
| US6452852B2 | Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration | Physics | 14 | Expired |
| US6351422B2 | Integrated memory having a differential sense amplifier | Physics | 12 | Expired |
| US6483768B2 | Current driver configuration for MRAM | Physics | 9 | Expired |
| US6664158B2 | Ferroelectric memory configuration and a method for producing the configuration | Electricity | 9 | Expired |
| US7423281B2 | Microelectronic device with a plurality of storage elements in serial connection and method of producing the same | Electricity | 8 | Expired |
| US6392918B2 | Circuit configuration for generating a reference voltage for reading a ferroelectric memory | Physics | 6 | Expired |
| US6137712A | Ferroelectric memory configuration | Physics | 5 | Expired |
| US6259641A | Integrated memory having sense amplifiers disposed on opposite sides of a cell array | Physics | 4 | Expired |
| US6906370B1 | Semiconductor component having a material reinforced contact area | Emerging Cross-Sectional Technologies | 3 | Expired |
| US6487128B2 | Integrated memory having memory cells and reference cells, and operating method for such a memory | Physics | 2 | Expired |
| US7254073B2 | Memory device having an array of resistive memory cells | Physics | 2 | Expired |
| US6459626B1 | Integrated memory having memory cells and reference cells, and corresponding operating method | Physics | 2 | Expired |
| US6803618B2 | MRAM configuration having selection transistors with a large channel width | Physics | 2 | Expired |
| US6538950B2 | Integrated memory and corresponding operating method | Physics | 1 | Expired |
| US6480055B2 | Decoder element for generating an output signal having three different potentials and an operating method for the decoder element | Electricity | 1 | Expired |
| US7158405B2 | Semiconductor memory device having a plurality of memory areas with memory elements | Physics | 1 | Expired |
| US6525974B2 | Integrated memory with redundancy | Physics | 1 | Expired |
| US6515890B2 | Integrated semiconductor memory having memory cells with a ferroelectric memory property | Physics | 0 | Expired |
| US6392445B2 | Decoder element for producing an output signal having three different potentials | Electricity | 0 | Expired |
| US6826075B2 | Random access semiconductor memory with reduced signal overcoupling | Electricity | 0 | Expired |
| US6711047B2 | Test circuit for an analog measurement of bit line signals of ferroelectric memory cells | Physics | 0 | Expired |
| US6538913B2 | Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration | Physics | 0 | Expired |
| US6645809B2 | Process for producing a capacitor configuration | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.