Low-pin-count chip package and manufacturing method thereof
US6261864A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.