Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor

US6261895A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• John A. Bracchitta · South Burlington, US
• Jed H. Rankin · South Burlington, US
• Anthony K. Stamper · Williston, US

Key dates

• Filing date: Jan 4, 1999
• Grant date: Jul 17, 2001
• Expiry date: Jan 4, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/022
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.