Dual bit isolation scheme for flash devices
US6261904A · kind A · utility
39Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jun 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.