Poly gate CD passivation for metrology control
US6261936A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film into a desired shape with a first sidewall and a second and opposite sidewall. A passivating oxide film is formed with a preselected thickness on the first and second sidewalls by oxidizing the silicon structure with a heated aqueous solution of ammonium hydroxide and hydrogen peroxide. Gate electrode formation with an oxide coating film of known thickness is provided. Linewidth metrology accuracy may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.