Patent · US Expired

Etch bias distribution across semiconductor wafer

US6262435A · kind A · utility

18Cited by

7References

6Claims

0Family size

Inventors

Marina V. Plat · San Jose, US
Luigi Capodieci · Sunnyvale, US
Scott A. Bell · San Jose, US
Todd P. Lukanc · San Jose, US

Key dates

Filing date	Dec 1, 1998
Grant date	Jul 17, 2001
Priority date	—
Expiry date	Dec 1, 2018

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/34
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.