Inventor · San Jose, CA, US

Scott A. Bell

105Patents
26h-index
84Co-inventors
93Inventor score

Filing activity: Nov 8, 1995 → Feb 17, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6211044A Process for fabricating a semiconductor device component using a selective silicidation reaction Electricity 161 Expired
US6773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning Electricity 157 Expired
US6500756B1 Method of forming sub-lithographic spaces between polysilicon lines Electricity 126 Expired
US6383952B1 RELACS process to double the frequency or pitch of small feature formation Electricity 76 Expired
US6184128A Method using a thin resist mask for dual damascene stop layer etch Electricity 74 Expired
US5767018A Method of etching a polysilicon pattern Electricity 67 Expired
US6020269A Ultra-thin resist and nitride/oxide hard mask for metal etch Electricity 65 Expired
US6541360B1 Bi-layer trim etch process to form integrated circuit gate structures Emerging Cross-Sectional Technologies 55 Expired
US6534418B1 Use of silicon containing imaging layer to define sub-resolution gate structures Electricity 51 Expired
US6664154B1 Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes Electricity 47 Expired
US6440640B1 Thin resist with transition metal hard mask for via etch application Electricity 43 Expired
US6764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Electricity 42 Expired
US6605514B1 Planar finFET patterning using amorphous carbon Electricity 42 Expired
US6884733B1 Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation Electricity 41 Expired
US6165695A Thin resist with amorphous silicon hard mask for via etch application Emerging Cross-Sectional Technologies 41 Expired
US6309926A Thin resist with nitride hard mask for gate etch application Electricity 39 Expired
US6653190B1 Flash memory with controlled wordline width Electricity 38 Expired
US6642148B1 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist Electricity 37 Expired
US6420097B1 Hardmask trim process Electricity 33 Expired
US5963841A Gate pattern formation using a bottom anti-reflective coating Electricity 33 Expired
US5965461A Controlled linewidth reduction during gate pattern formation using a spin-on barc Emerging Cross-Sectional Technologies 33 Expired
US6127070A Thin resist with nitride hard mask for via etch application Electricity 32 Expired
US6107172A Controlled linewidth reduction during gate pattern formation using an SiON BARC Emerging Cross-Sectional Technologies 31 Expired
US6750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance Electricity 31 Expired
US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation Electricity 30 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.