Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit
US6263461A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Jul 17, 2001 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318522
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic. Thus, the built in test circuit of the present invention is able to perform precise isolated testing on the memory block and perform precise isolated testing on the shadow logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.