Flexible semiconductor interconnect fabricated by backslide thinning
US6263566A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1999 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | May 3, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49224
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An interconnect for testing semiconductor components includes a thinned substrate, and first contacts on the substrate for electrically engaging second contacts on the components. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. The thinned substrate has a thickness that is substantially less than a thickness of the components being tested. The thinned substrate can flex upon application of a biasing force by the testing apparatus, permitting the first contacts to move in the z-direction to accommodate variations in the planarity of the second contacts. For fabricating the interconnect, the first contacts are formed on the substrate, and then covered with a protective mask. With the mask in place, the substrate can be thinned by grinding, chemical mechanical planarization, or alternately by etching a backside of the substrate. Other process steps such as via formation and backside metallization can also be performed with the protective mask in place. The protective mask can then…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.