Method of fabrication of a novel flash integrated circuit

US6265292A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Krishna K. Parat · Palo Alto, US
• Raghupathy Giridhar · San Jose, US
• Cheng C. Hu · San Jose, US
• Daniel Xu · Mountain View, US
• Yudong Kim · Cupertino, US
• Glen Wada · Fremont, US

Key dates

• Filing date: Jul 12, 1999
• Grant date: Jul 24, 2001
• Expiry date: Jul 12, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/44

Abstract

A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.