Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant
US6265749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor is provided having a metal silicide gate spaced above a semiconductor substrate by a high-dielectric-constant ceramic gate dielectric. The entire gate conductor is preferably composed of a metal silicide. In an embodiment, the metal silicide is cobalt silicide and the ceramic gate dielectric is barium strontium titanate, lead lanthanum zirconate titanate barium zirconate titanate, cerium oxide, or tin oxide. In another embodiment, the ceramic gate dielectric has nitrogen atoms incorporated therein. The transistor may also include dielectric spacers adjacent opposed sidewall surfaces of the gate conductor, lightly doped drain regions arranged underneath the spacers, and source and drain regions arranged adjacent the lightly doped drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.