Dual rail dynamic flip-flop with single evaluation path
US6265923A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2000 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Apr 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01855
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic flip-flop circuit that operates in a pre-charge phase and an evaluation phase allows for implementation of multiple-input logic functions without sacrificing performance by using a single evaluation path to generate its output signals. In one embodiment, the dynamic flip-flop circuit includes input logic that receives a clock signal and one or more data input signals. The clock signal defines the pre-charge phase and the evaluation phase of the flip-flop circuit. The input logic has an output terminal connected to a first output buffer circuit, which in turn drives the flip-flop circuit's Q output signal. The output terminal of the input logic is combined with the clock signal in a logic gate having an output terminal connected to a second output buffer circuit, which in turn drives the flip-flop circuit's complementary output signal Q. During the pre-charge phase, the input logic forces the Q output signal to a first logic state via the first output buffer, and the logic gate forces the Q output signal to logic low via the second output buffer. During the evaluation phase, the input logic generates a logic signal in response to a predetermined logic function of its one o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.