Three terminal non-volatile memory element
US6266269A · kind A · utility
89Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2000 |
| Grant date | Jul 24, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three terminal non-volatile memory element includes a standard (low voltage) CMOS transistor, i.e. a storage transistor, having a drain coupled to a read bit line and a source connected to ground. The storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. Of importance, in submicron technology, the source and drain regions of the storage transistor merge, thereby providing a highly reliable, conductive path. Thus, the state of the memory cell can be advantageously read solely via the read bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.