Three dimensional package and architecture for high performance computer
US6268238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Jul 8, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The packgage allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.