Efficient fabrication process for dual well type structures
US6268250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
Abstract
An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.