Patent · US Expired

Method of forming a transistor having a low-resistance gate electrode

US6268257A · kind A · utility

24Cited by

5References

28Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Karsten Wieczorek · Dresden, DE
Michael Raab · Salem, DE
Rolf Stephan · Dresden, DE

Key dates

Filing date	Apr 25, 2000
Grant date	Jul 31, 2001
Priority date	—
Expiry date	Apr 25, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/0227
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.