Rolf Stephan
38Patents
9h-index
28Co-inventors
71Inventor score
Filing activity: Apr 25, 2000 → Oct 18, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6881641B2 | Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same | Electricity | 125 | Expired |
| US7297994B2 | Semiconductor device having a retrograde dopant profile in a channel region | Electricity | 118 | Active |
| US6306698A | Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same | Electricity | 29 | Expired |
| US6566718B2 | Field effect transistor with an improved gate contact and method of fabricating the same | Electricity | 26 | Expired |
| US6268257A | Method of forming a transistor having a low-resistance gate electrode | Electricity | 24 | Expired |
| US7608499B2 | Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same | Electricity | 19 | Active |
| US7325224B2 | Method and system for increasing product yield by controlling lithography on the basis of electrical speed data | Physics | 13 | Expired |
| US6620718B1 | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device | Electricity | 13 | Expired |
| US6423634B1 | Method of forming low resistance metal silicide region on a gate electrode of a transistor | Electricity | 10 | Expired |
| US7217657B2 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device | Electricity | 9 | Expired |
| US6593197B2 | Sidewall spacer based fet alignment technology | Electricity | 7 | Expired |
| US8796807B2 | Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials | Electricity | 7 | Active |
| US6846708B2 | Semiconductor device having improved doping profiles and a method of improving the doping profiles of a semiconductor device | Electricity | 6 | Expired |
| US6798028B2 | Field effect transistor with reduced gate delay and method of fabricating the same | Electricity | 6 | Expired |
| US7238578B2 | Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions | Electricity | 5 | Expired |
| US6673665B2 | Semiconductor device having increased metal silicide portions and method of forming the semiconductor | Electricity | 5 | Expired |
| US8846513B2 | Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill | Electricity | 5 | Active |
| US8735236B2 | High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology | Electricity | 5 | Active |
| US8119461B2 | Reducing the creation of charge traps at gate dielectrics in MOS transistors by performing a hydrogen treatment | Electricity | 4 | Active |
| US7226859B2 | Method of forming different silicide portions on different silicon-containing regions in a semiconductor device | Electricity | 3 | Expired |
| US6492210B2 | Method for fully self-aligned FET technology | Electricity | 3 | Expired |
| US7605045B2 | Field effect transistors and methods for fabricating the same | Electricity | 3 | Active |
| US6770552B2 | Method of forming a semiconductor device having T-shaped gate structure | Electricity | 3 | Expired |
| US7115464B2 | Semiconductor device having different metal-semiconductor portions formed in a semiconductor region and a method for fabricating the semiconductor device | Electricity | 2 | Expired |
| US8871586B2 | Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material | Emerging Cross-Sectional Technologies | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.