Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects
US6268269A · kind A · utility
36Cited by
10References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for an oxide layer with reduced interface-trapped charges, which is applicable to the fabrication of a gate oxide layer of a flash memory device, is described. The method includes conducting a first inert ambient annealing process, followed by growing an oxide layer on the silicon substrate. A second inert ambient annealing process is then conducted on the oxide layer. Carbon ions are then incorporated into the interface between the oxide layer and the silicon substrate, followed by a third ambient annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.