Area array air gap structure for intermetal dielectric application
US6268276A · kind A · utility
39Cited by
6References
35Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 21, 1998 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a "holes everywhere" or a "reverse metal holes" mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.