Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom
US6268277A · kind A · utility
33Cited by
10References
2Claims
0Family size
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Key dates
| Filing date | Jul 16, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Jul 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The method involves forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric region, forming an air gap at least partially within the dielectric region, and sealing the air gap to entrap the air gap between the first and second metal regions thereby reducing intralevel capacitance between the first and second metal regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.