Semiconductor test structure with intentional partial defects and method of use
US6268717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1999 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. A number of intentional partial defects may be formed at predetermined locations along the test structure. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.