Optical proximity correction method and apparatus
US6269472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Jul 31, 2001 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31769
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.