Method for fabricating a buried vertical split gate memory device with high coupling ratio
US6271088A · kind A · utility
11Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2001 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method of fabricating a buried vertical split gate memory cell is disclosed. First, a first trench is created in an SOI substrate for accommodating a floating gate. A second trench, having a smaller width than that of the first trench, is then created at the bottom of the first trench for accommodating a word line/control gate. Simultaneously, a silicon sidewall step structure is produced and functions as a vertical channel of the buried vertical split gate memory cell, wherein the vertical control gate channel length (L.sub.CG) and the floating gate channel length (L.sub.FG) is 0.25 micrometers and about 3.5 nm, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.