Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
US6271102A · kind A · utility
63Cited by
22References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T83/0581
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.