Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
US6271133A · kind A · utility
17Cited by
12References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1999 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi.sub.2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi.sub.2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi.sub.2 serves as the electrical gate contact point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.