Data processing system with master and slave devices and asymmetric signal swing bus
US6272577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1997 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Oct 30, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. A resynchronization circuit allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation so that each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. Redundant memory modules are included to replace defective memory modules, and replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.