System and method for improving processor read latency in a system employing error checking and correction
US6272651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1998 |
| Grant date | Aug 7, 2001 |
| Priority date | — |
| Expiry date | Aug 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol. Also, all bus master devices (CPUs) on the processor bus may perform the same data integrity protocol. When a CPU requests read data from main memory, the bus interface unit forwards the read data and error information unmodified to the processor bus bypassing the data integrity logic within the system interface unit. However, the system interface unit may still perform the data integrity protocol in parallel with the requesting CPU so that the system interface unit may track errors and possibly notify the operating system or other error control software of any errors. In this manner processor read latency is improved without sacrificing data integrity. Furthermore, the system interface unit may still track errors on processor reads. If the read request is from a device on a peripheral bus (AGP or PCI bus), then the system interface unit performs the data integrity protocol on the data and error bits before forwarding the read da…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.