Method of reducing defects in I/C card and resulting card
US6274291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1998 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1394
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.