Method for forming a capacitor electrode
US6274424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.